Field
This disclosure relates generally to memory systems, and more specifically, to a memory system having a source bias circuit.
Related Art
It is desirable to reduce leakage currents in memories during standby in order to conserve power and achieve improved data retention. Even when a memory is in a “standby” or “off” state, each device in the memory array which is “off” exhibits leakage current. Although this leakage current is small, for a large memory array, the total leakage current can add up to a more significant amount, contributing more significantly to power loss, which is especially problematic in battery operated devices, such as hand-held mobile devices.
Leakage reduction in memory arrays can be achieved by techniques such as applying a reverse body bias (RBB) to the well connection of the memory array transistors (e.g. of the pulldown and passgate N-type Metal-Oxide-Semiconductor (NMOS) devices located in an isolated p-well). Further leakage reduction can be achieved by applying source biasing to the array devices (e.g. to the pulldown and pullup devices of a memory cell). This is achieved using a diode-connected Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) outside of the isolated well of the memory array, connected between the sources of the array devices and ground. However, the combination of these techniques leads to diminished return of the source biasing. That is, because the reverse body bias reduces the leakage of the array, the load on the diode-connected MOSFET is also reduced, which in turn reduces the source bias voltage, causing a degradation of the leakage reduction. Therefore, a need exists for an improved source bias when the memory array is reverse body biased.